1. Field of the Invention
The present invention relates to an internal voltage generating circuit, which generates an internal power supply voltage for a LSI. More particularly, it relates to an internal voltage generating circuit in which a stable internal power supply voltage for operation can be warranted within a wide range of an external supply voltage during normal operation and a higher internal power supply voltage can be accurately generated during stress operation.
2. Description of the Related Art
A first requirement of an internal voltage generating circuit, which generates an internal supply voltage in an LSI, is to generate a constant internal power supply voltage required for normal operation in internally provided circuits when an externally supplied power supply voltage is within a range warranted in a catalog. Therefore, an internal power supply voltage is generated by dropping the externally supplied power supply voltage. A second requirement is to give a function for rising the internal power supply voltage higher than that when normal operation, when executing an acceleration test involving stress operations to remove an initial defection on a LSI. In other words, the internal power supply voltage in the acceleration test mode requires a prescribed higher voltage.
The conventionally employed power supply voltage of 5 V is transiting to 3.3 V. In recent years, it is transiting to 2.5 V. In this case, only one of the voltages 5 V, 3.3 V and 2.5 V is employed as a power source on a motherboard, on which a LSI is mounted. That requires a LSI such as a memory to adapt every voltage.
FIG. 9 shows a conventional internal voltage generating circuit. The circuit generates the above-described internal power supply voltage during normal operation and an internal power supply voltage during acceleration test. The internal voltage generating circuit shown in FIG. 9 includes a first voltage generating circuit 10, a differential amplifying circuit 12, a second voltage generating circuit 15, a differential amplifying circuit 14 and a synthesis circuit 13. The first voltage generating circuit 10 generates a reference voltage V.sub.FLAT, and the second voltage generating circuit 15 generates a voltage V.sub.BI, depends on an external power supply voltage level V.sub.DD. Further, the synthesis circuit 13 outputs the higher one of the reference voltage V.sub.FLAT and the voltage V.sub.BI as an internal power supply voltage V.sub.INT. The external power supply voltage V.sub.DD is supplied from an externally provided device, and the internal power supply voltage V.sub.INT has a constant voltage during normal operation and a higher voltage during acceleration test operation. The reference voltage V.sub.FLAT is employed as an internal power supply when the external power supply voltage V.sub.DD is within a warranty voltage range. The voltage V.sub.BI goes to a higher level according to the external power supply voltage V.sub.DD, which goes to a higher level during acceleration test.
FIG. 10 shows an operational explanatory diagram of the internal voltage generating circuit of FIG. 9. The axis of abscissa shows an external power supply voltage V.sub.DD and the axis of ordinates shows a voltage value V. The bold line shows a voltage V.sub.DD when the external power supply voltage V.sub.DD is changed, which is a simple line having a slope angle of 1. The broken line shows a reference voltage V.sub.FLAT when the external power supply voltage V.sub.DD is changed. The reference voltage V.sub.FLAT is 2.5 V when the external power supply voltage V.sub.DD is within or around 3.0 V to 3.6 V, which is warranted in a catalog, for example. The chain line shows a voltage V.sub.BI. When the external power supply voltage V.sub.DD exceeds over threshold values of P type transistors P10 and P11, the voltage V.sub.BI rises at a slope angle, which is decided according to a resistance value R12, as the external power supply voltage V.sub.DD rises. Then, the internal power supply voltage V.sub.INT goes to the higher one of the reference voltage V.sub.FLAT and the voltage V.sub.BI, as shown by the reticulate section of FIG. 10.
The first voltage generating circuit of FIG. 9 generates a sum of thresholds of N type transistors Q1 and Q2 as a reference voltage V.sub.FLAT, which can be expressed as: V.sub.FLAT (=V.sub.th1 +V.sub.th2). In this circuit, when the threshold voltages of the transistors Q1 and Q2 fall according to the temperature fluctuation, conductivity of the transistor Q2 rises. The reference voltage V.sub.FLAT falls as an impedance of the transistor Q2 is decreased. According to that, the conductivity of the transistor Q1 falls, currents I1 flowing through a resistor R11 decreases, and the voltage of a gate of the transistor Q2 drops. As a result, an impedance of the transistor Q2 is increased, and therefore, it becomes possible to keep the voltage V.sub.FLAT constant. It is also possible to keep the voltage V.sub.FLAT constant when the external power supply voltage V.sub.DD is changed in the same way.
Additionally, a differential amplifying circuit 12, which is constituted by P type transistors P3 to P5 and N type transistors Q3 to Q5, operates so that the gate voltages of the transistors Q3 and Q4 be coincident. Therefore, the same potential as the reference voltage V.sub.FLAT is maintained at a node n1.
On the other hand, the second voltage generating circuit 15, as mentioned above, generates a voltage V.sub.BI, which rises at a slope angle of a resistance value R12, from the sum of the threshold values 2 Vth of the P type transistors P10 and P11. The differential amplifying circuit 14 operates so that the gate voltages of the N type transistors Q12 and Q13 be coincident, similarly to those of the differential amplifying circuit 12. As a result, the same potential as the voltage V.sub.BI can be maintained at the node n1. However, the synthesis circuit 13 selects the higher one of the reference voltage V.sub.FLAT and the voltage V.sub.BI as an internal power supply voltage V.sub.INT of the node n1.
As shown in FIG. 10, if the external power supply voltage V.sub.DD is between 3.0 V and 3.6 V, which is a voltage range warranted in a catalog, the internal power supply voltage V.sub.INT maintains the reference voltage V.sub.FLAT. If the external power supply voltage V.sub.DD exceeds over the range warranted in a catalog, for example, 4.5 V, when executing an acceleration test, the internal power supply voltage V.sub.INT is controlled so as to be a high voltage V.sub.BI for acceleration test, for example, 3.5 V.
Although the internal power supply voltage for acceleration test requires the voltage V.sub.BI of almost 3.5 V, if the voltage is too high, the voltage breaks internal circuits. On the contrary, if the voltage is too low, the LSI where an initial defection occurs can not be accurately detected because of insufficient stress at the acceleration test. Therefore, the internal power supply voltage at the acceleration test should be accurately generated at a pinpoint. In the second voltage generating circuit 15 of the internal voltage generating circuit, the voltage V.sub.BI is decided depending on the threshold voltages of the P type transistors P10 and P11 and the resistance value R12. However, the threshold values of the P type transistors P10 and P11 are generally dispersed depending on the processes. Therefore, it is difficult to accurately generate the voltage V.sub.BI (3.5 V) of the internal power supply voltage at the acceleration test in the conventional internal voltage generating circuit.
To avoid the problem of the dispersion of the thresholds depending on the processes, it can be assumed that resistors are provided instead of the P type transistors P10 and P11 of the second voltage generating circuit 15 of FIG. 9 to generate the voltage V.sub.BI by subdividing the external power supply voltage V.sub.DD according to the resistances. However, the voltage has a character like the voltage V.sub.BI 2 shown in FIG. 10, and therefore, it becomes impossible to generate enough high internal power supply voltage for acceleration test. It is further impossible to keep the internal power supply voltage V.sub.INT constant within a catalog warranted voltage range.